Apparatus for handling out-of-order exceptions in pipe-lined parallel processing that prevents execution of all instructions behind exception predicted instruction and aborts if exception actually occurs
September 2, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData processing apparatus and method employing instruction pipelining Data processing apparatus and method employing collision detection and prediction Vector processing apparatus including means for identifying the occurrence of exceptions in the processing of vector elements Method for implementing synchronous pipeline exception recovery Method and apparatus for precise floating point exceptions Method and apparatus for dynamically controlling each stage of a multi-stage pipelined data unit Method and apparatus for handling out of order exceptions in a pipelined data unit Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures Data processing system for concurrent dispatch of instructions to multiple functional units Paired instruction processor precise exception handling mechanism InventorApplicationNo. 863180 filed on 04/03/1992US Classes:712/219, Reducing an impact of a stall or pipeline bubble712/206, Of multiple instructions simultaneously712/207, Prefetching712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION712/244, Exeception processing (e.g., interrupts and traps)712/246, Plural microsequencers (e.g., dual microsequencers)714/50State out of sequenceExaminersPrimary: Lee, Thomas C.Assistant: Kim, Ki S. Attorney, Agent or FirmForeign Patent References
International ClassesG06F 009/302G06F 009/38 Foreign Application Priority Data1991-04-05 JPAbstractA parallel processing control apparatus comprises processing blocks each providing an equal function and incorporating pipeline operation units; a status register for storing statuses of the processing blocks; an instruction feeder for simultaneously allocating instructions to the processing blocks; a flagging unit for setting a flag for a corresponding one of the processing blocks to indicate that at least one instruction fed to another of the processing blocks and positioned, on a sequential model, behind an instruction being processed in the flagged processing block has been processed or passed through a specific stage; a flag holder for holding the flag; and a write controller for selecting a processing block whose status is to be written in the status register.Other References
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