Cache coherency method and system employing serially encoded snoop responses
November 29, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesHardware implemented cache coherency protocol with duplicated distributed directories for high-performance multiprocessors Multiport cache memory control unit including a tag memory having plural address ports and a snoop address part Cache coherency method and apparatus for a multiple path interconnection network Computer bus arbitration for N processors requiring only N unidirectional signal leads Competitive snoopy caching for large-scale multiprocessors Method and apparatus for concurrency of bus operations Instruction and data cache with a shared TLB for split accesses and snooping in the same clock cycle Patent #: 5440707 InventorsApplicationNo. 564888 filed on 11/29/1995US Classes:711/146SnoopingExaminersPrimary: Chan, Eddie P.Assistant: Bragdon, Reginald G. Attorney, Agent or FirmForeign Patent References
International ClassG06F 013/16AbstractA cache coherency method and system are provided for ensuring coherency of accessed data for each bus master of a plurality of bus masters in a processing system, wherein at least some bus masters have a cache means connected to a system bus, which provides communication to a main memory for access of data stored therein. Each of these at least some bus masters also includes snoop monitor logic, e.g., residing within a bus interface unit (BIU), for monitoring the presence of a coherent memory transaction on the system bus and for broadcasting in response thereto a unidirectional snoop response signal with reference to the bus master's caching means whenever the coherent memory transaction is initiated by other than that bus master. The snoop monitors are electrically interconnected, with each snoop monitor receiving at a separate signal input the unidirectional snoop response signal broadcast by each other snoop monitor of the plurality of snoop monitors. Each snoop response signal broadcast comprises one snoop response of a set of N predetermined snoop responses, each snoop response being M binary bits in length with a single bit of each snoop response being broadcast in a single clock cycle of the processing system such that M binary bits are preferably transferred over M consecutive clock cycles, wherein Mࣙ1 and N=2M.Other References
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