Implementation of a selected instruction set CPU in programmable hardware
May 24, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMulti-functional arithmetic and logical unit Data processing apparatus providing autoloading of memory pointer registers Microprocessor architecture for improved chip testability Programmable logic device with subroutine stack and random access memory Crossbar switch connected modular multiprocessor system with processor timing relationship selected and synchronized to be appropriate for function being performed Functionally complete family of self-timed dynamic logic circuits Patent #: 5208490 InventorAssigneeApplicationNo. 449563 filed on 05/24/1995US Classes:716/1CIRCUIT DESIGNExaminersPrimary: Teska, Kevin J.Assistant: Mohamed, Ayni Attorney, Agent or FirmInternational ClassesG06F 009/00G06F 015/177 AbstractA method of designing a CPU for implementation in a configurable hardware device by identifying a series of operations in a logic scheme which are suitable for implementation in the device, identifying an executable function and any needed parameters in the logic scheme, identifying the logic flow in the scheme, providing for at least two connected system resources to implement the logic scheme, selecting an op code, and providing a way to implement the various components needed to call and execute the function according to the logic scheme. A useful op code may invoke a system resource, implement the logic scheme, pass a parameter to the function, or invoke the function. The configurable hardware system can function as a CPU, using logic resources including a next address RAM, one or more registers, a function execution controller, and one or more busses for passing signals and data between the components and functions. | |
