Data processor with controlled burst memory accesses and method therefor
December 21, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod and apparatus for interfacing buses of different sizes Bus master having burst transfer mode Bus master having selective burst initiation Microprocessor bus interface unit which changes scheduled data transfer indications upon sensing change in enable signals before receiving ready signal Method of transferring burst data in a microprocessor Bus controller for adjusting a bus master to a bus slave High performance burst read data transfer operation Data processor with bus-sizing function Cache including decoupling register circuits Method for synchronously accessing memory Patent #: 5502835 InventorsAssigneeApplicationNo. 363423 filed on 12/21/1994US Classes:711/154, Control technique711/157, Interleaving711/169Memory access pipeliningExaminersPrimary: Harvey, Jack B.Assistant: Pancholi, Jigar Attorney, Agent or FirmInternational ClassG06F 012/00AbstractA data processor (21) includes an external bus interface circuit (33) responsive to two internal bus master devices (30, 34) to perform either a fixed or a variable burst access. The data processor (21) activates an external control signal to indicate whether a burst access is a fixed or a variable burst access. The data processor (21) indicates the port size of the accessed memory region by providing a port size signal to the external bus interface circuit (33). The external bus interface circuit (33) is responsive to the port size signal to break up the burst cycle into two or more burst cycles on the external bus (22, 23), if the accessed location corresponds to a memory (24) with a different port size than the internal bus (31).Other References
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