Patent ReferencesMultiprocessor mechanism for handling channel interrupts Multiprocessor intercommunication system and method Multiprocessor computer system Shared resource locking apparatus Parallel process controller Concurrent hypercube system with improved message passing Data processing system for array computation Multi-level bus access for multiple central processing unit Interprocessor bus switching system for simultaneous communication in plural bus parallel processing system Synchronized parallel processing with shared memory InventorsApplicationNo. 641947 filed on 05/02/1996US Classes:709/221, Reconfiguring345/505, Parallel processors (e.g., identical processors)345/541, Shared memory709/208, MASTER/SLAVE COMPUTER CONTROLLING709/216, Accessing another computer's memory710/31, Transfer direction selection710/38, Path selection710/48, Input/Output interrupting710/266, Programmable interrupt processing712/15ReconfiguringExaminersPrimary: Black, Thomas G.Assistant: Homere, Jean R. Attorney, Agent or FirmForeign Patent References
International ClassesG06F 015/163G06F 017/00 Foreign Application Priority Data1991-03-14 JPAbstractA parallel computer having a plurality of cluster buses 2 which are connected to the processor (PE) 1 via the selectors 6. The selectors 6 maintain the same condition until the next instruction is received. In this system, the clusters 11 are reconstructed at appropriate timing during the operation of the processor, thus allowing the number of processors PEs in a cluster to be exchanged in response to variation in the process load allocated to each cluster 11. Accordingly, the resources of the computer are used more effectively. The execution environment of each process may be independent. Real time execution of each process can be assured.Other References
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