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Method and structure for front-side gettering of silicon-on-insulator substrates

Patent 5646053 Issued on July 8, 1997. Estimated Expiration Date: Icon_subject December 20, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Process of gettering semiconductor devices
Patent #: 4561171
Issued on: 12/31/1985
Inventor: Schlosser

Gettering process with multi-step annealing and inert ion implantation
Patent #: 4885257
Issued on: 12/05/1989
Inventor: Matsushita

Method of producing a substrate having semiconductor-on-insulator structure with gettering sites
Patent #: 5194395
Issued on: 03/16/1993
Inventor: Wada

Method of manufacturing SOI semiconductor device
Patent #: 5308776
Issued on: 05/03/1994
Inventor: Gotou

Method for thinning SOI films having improved thickness uniformity
Patent #: 5318663
Issued on: 06/07/1994
Inventor: Buti, et al.

Semiconductor substrate for gettering
Patent #: 5397903
Issued on: 03/14/1995
Inventor: Hirose

Method of manufacturing substrate having semiconductor on insulator
Patent #: 5441899
Issued on: 08/15/1995
Inventor: Nakai, et al.

SOI (silicon on insulator) substrate with enhanced gettering effects
Patent #: 5443661
Issued on: 08/22/1995
Inventor: Oguro, et al.

Method of making a getterer for multi-layer wafers Patent #: 5478758
Issued on: 12/26/1995
Inventor: Easter

Inventors

Application

No. 575458 filed on 12/20/1995

US Classes:

438/402, And gettering of substrate257/E21.23, With simultaneous mechanical treatment, e.g., chemical-mechanical polishing (EPO)257/E21.32, Of silicon on insulator (SOI) (EPO)438/476By layers which are coated, contacted, or diffused

Examiners

Primary: Dang, Trung

Attorney, Agent or Firm

International Class

H01L 021/306

Abstract

A method of gettering an SOI wafer from the front side of the wafer includes depositing a gettering layer, such as polysilicon, on the SOI layer and annealing the SOI wafer with the gettering layer in place. A polish stop structure, which can be deposited before or after the gettering layer, provides a means for selectively removing the gettering layer from the SOI wafer without damaging the surface or eroding the thickness of the SOI layer.

Other References

  • Jablonski, et al., "Gettering of Cu and Ni Impurities in Simox Wafers", J. Electrochem. Soc., vol. 142, No. 6, Jun. 1995, pp. 2059-2066
  • H. D. Chiou, et al., "Gettering of Bonded SOI Layers", Abstrat No. 194, Discrete and Materials Technology Group, Motorola, Inc. pp. 325-326
  • Horiuchi, et al., "One-Decade Reduction of pn-Junction Leakage Current Using Poly-Si Interlayered SOI Structures", IEEE 1993, 34.5.1-34.5.4
  • Rozgonyi, et al., "Low Temperature Impurity Gettering for Giga-Scale Integrated Circuit Technology", Journal Reprint, SRC Pub C94132, Contract 93-MJ-533, Mar. 1994
  • U.S. Patent Application, Serial No. 08/575,421 Entitled: "Method and Structures for Lateral Gettering of Silicon-on-Insulator Substrates", Devendra Sadana, et al., Docket No. FI9-95-155, Filed Dec. 20, 199
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