Linear list based DMA control structure
Patent 5644784 Issued on July 1, 1997. Estimated Expiration Date: 
March 3, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
March 3, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData processing system capable of performing a direct memory access transfer of data stored in a physical area in a memory System for DMA block data transfer based on linked control blocks Method and apparatus for dynamic chaining of DMA operations without incurring race conditions Adapters with descriptor queue management capability Patent #: 5448702 InventorApplicationNo. 398439 filed on 03/03/1995US Classes:710/24, By command chaining710/35Burst data transferExaminersPrimary: Auve, Glenn A.Attorney, Agent or FirmInternational ClassG06F 013/28AbstractLinear list based direct memory access (DMA) control structure for controlling a DMA processor through a linear list of DMA descriptors in memory. A descriptor entry is deposited at the end of the linear list. Each descriptor entry has an address associated with their location in the linear list. A pointer to the linear list points to a single location in the linear Fist. A next descriptor entry is accessed by decrementing the address corresponding to the single location. The descriptor entries are read from the linear list of DMA descriptors DMA transfers are performed. | |
