Single chip network router

Patent 5640399 Issued on June 17, 1997. Estimated Expiration Date:

September 18, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

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Inventors

Assignee

LSI Logic Corporation

Application

No. 529656 filed on 09/18/1995

US Classes:

370/392, Processing of address header for routing, per se370/402, Bridge between bus systems370/466Converting between protocols

Examiners

Primary: Chin, Wellington
Assistant: Vu, Huy D.

Attorney, Agent or Firm

Poms, Smith, Lande & Rose

International Classes

H04J 003/14
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Abstract

A single chip router for a multiplex communication network comprises a packet memory for storing data packets, a Reduced Instruction Set Computer (RISC) processor for converting the packets between a Local Area Network (LAN) protocol and a Wide Area Network (WAN) protocol, a LAN interface and a WAN interface. A Direct Memory Access (DMA) controller transfers packets transferring packets between the packet memory and the LAN and WAN interfaces. A packet attribute memory stores attributes of the data packets, and an attribute processor performs a non-linear hashing algorithm on an address of a packet being processed for accessing a corresponding attribute of said packet in the packet attribute memory. An address window filter identifies the address of a packet being processed by examining only a predetermined portion of said address, and can comprise a dynamic window filter or a static window filter.