Integrated circuit employing dummy conductors for planarity
Method of making reliable metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layers Patent #: 5476817
ApplicationNo. 593900 filed on 01/30/1996
US Classes:438/633, Simultaneously by chemical and mechanical means257/E21.244, Involving dielectric removal step (EPO)438/645, Having planarization step438/691, Combined mechanical and chemical material removal438/926DUMMY METALLIZATION
ExaminersPrimary: Bowers, Charles L. Jr.
Assistant: Gurley, Lynne A.
Attorney, Agent or Firm
International ClassesH01L 021/302
AbstractA method of commonizing the pattern density of topography for different layers of semiconductor wafers to improve the Chemical Mechanical Polishing process used during wafer processing is disclosed. In order to achieve a predetermined pattern density of topography on the surface of a wafer, dummy raised lines are inserted as necessary into gaps between active conductive traces on a trace layer. In some embodiments, the predetermined pattern density is in the range of approximately 40% to 80%. In some applications, both the active conductive traces and the dummy raised lines are formed from a metallic material that is deposited in one single step with an insulating layer deposited over both the active conductive traces and the dummy raised lines prior to the Chemical Mechanical Polishing process. In other applications, the dummy raised lines are formed from the insulating layer.