Multiprocessor integrated circuit with video refresh logic employing instruction/data caching and associated timing synchronization
Patent 5638531 Issued on June 10, 1997. Estimated Expiration Date: 
June 7, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 7, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDual mode SIMD/MIMD processor providing reuse of MIMD instruction memories as data memories when operating in SIMD mode Imaging computer system and network Patent #: 5410649 InventorsApplicationNo. 475664 filed on 06/07/1995US Classes:711/123, User data cache and instruction data cache345/502, Plural graphics processors711/121Private cachesExaminersPrimary: Kim, MatthewAttorney, Agent or FirmInternational ClassG06F 012/08AbstractA digital data handling system handling display signal streams has a video processor which is capable of high performance due to vector processing and special addressing modes. The video processor is a single VLSI device having a plurality of processors, each of which has associated instruction and data caches, which are joined together by a wide data bus formed on the same substrate as the processors. Any graphics subsystem must be able to support a variety of video formats, causing video refresh logic to become complicated. Such potential complications are avoided by the provision of a simple, general purpose hardware refresh system based on the direct color graphics frame buffer, with the broader range of services being provided by emulation using one of the processors included in the device.Other References
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