Method and system for aligning the phase of high speed clocks in telecommunications systems
June 10, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesPhase comparators Sample-and-hold phase detector for use in a phase locked loop Extended range phase detector Dual state phase detector having frequency steering capability Digital phase aligner and method for its operation All digital phase locked loop Digital phase lock clock generator without local oscillator Phase detector and methodology Patent #: 5376847 InventorAssigneeApplicationNo. 136339 filed on 10/14/1993US Classes:375/357, Synchronization failure prevention327/5, With input derived from feedback327/7, With reference signal327/12, With logic or bistable circuit327/149, With variable delay means327/156, Phase lock loop327/161, With delay means327/163, By phase375/371, Phase displacement, slip or jitter correction375/373, Phase locking375/376Phase locked loopExaminersPrimary: Chin, StephenAssistant: Le, Amanda T. Attorney, Agent or FirmInternational ClassH04L 007/00AbstractA method and system are provided for detecting and measuring a phase difference, linearly over a range of 360°, between the output signals from a primary stratum clock module (100) and a standby stratum clock module (120) in a telecommunications system, calculating the amount of time needed to delay the standby clock signal (ø2) enough to cancel the phase difference, and controlling a digital delay line (132) to shift the phase of the standby clock signal (ø2) accordingly and thereby cancel the phase difference. Both the frequency and phase alignments of the two clocks are thus maintained. Therefore, when the system or user switches operations from the primary stratum clock module (100) to the standby stratum clock module (120), phase-related transients are not generated, which results in a significant increase in the overall performance and reliability of the system.Field of SearchSynchronization failure preventionPhase displacement, slip or jitter correction Phase locking With charge pump or up and down counters With frequency detector and phase detector Phase locked loop Particular error voltage control (e.g., intergrating network) Signal or phase comparator With logic or bistable circuit Comparison between plural inputs (e.g., phase angle indication, lead-lag discriminator, etc.) Edge sensing With input derived from feedback With reference signal With variable delay means Phase lock loop With delay means By phase | |
