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US Patent 5638410 - Method and system for aligning the phase of high speed clocks in telecommunications systems
US Patent Issued on June 10, 1997
Estimated Patent Expiration Date:
June 10, 2014Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
Estimated Patent Expiration Date:
June 10, 2014Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.AbstractA method and system are provided for detecting and measuring a phase difference, linearly over a range of 360°, between the output signals from a primary stratum clock module (100) and a standby stratum clock module (120) in a telecommunications system, calculating the amount of time needed to delay the standby clock signal (ø2) enough to cancel the phase difference, and controlling a digital delay line (132) to shift the phase of the standby clock signal (ø2) accordingly and thereby cancel the phase difference. Both the frequency and phase alignments of the two clocks are thus maintained. Therefore, when the system or user switches operations from the primary stratum clock module (100) to the standby stratum clock module (120), phase-related transients are not generated, which results in a significant increase in the overall performance and reliability of the system. | InventorAssigneeApplicationNo. 136339 filed on 10/14/1993US Classes:375/357, Synchronization failure prevention327/5, With input derived from feedback327/7, With reference signal327/12, With logic or bistable circuit327/149, With variable delay means327/156, Phase lock loop327/161, With delay means327/163, By phase375/371, Phase displacement, slip or jitter correction375/373, Phase locking375/376Phase locked loopField of Search375/357, Synchronization failure prevention375/371, Phase displacement, slip or jitter correction375/373, Phase locking375/374, With charge pump or up and down counters375/375, With frequency detector and phase detector375/376, Phase locked loop331/17, Particular error voltage control (e.g., intergrating network)331/25, Signal or phase comparator327/12, With logic or bistable circuit327/3, Comparison between plural inputs (e.g., phase angle indication, lead-lag discriminator, etc.)327/24, Edge sensing327/5, With input derived from feedback327/7, With reference signal327/149, With variable delay means327/156, Phase lock loop327/161, With delay means327/163By phaseExaminersPrimary: Chin, StephenAssistant: Le, Amanda T. Attorney, Agent or FirmUS Patent References4851784, Phase comparatorsIssued on: 07/25/1989 Inventor: Wells , et al.4864252, Sample-and-hold phase detector for use in a phase locked loop Issued on: 09/05/1989 Inventor: Heck4902920, Extended range phase detector Issued on: 02/20/1990 Inventor: Wolaver4959617, Dual state phase detector having frequency steering capability Issued on: 09/25/1990 Inventor: Martin5081655, Digital phase aligner and method for its operation Issued on: 01/14/1992 Inventor: Long5109394, All digital phase locked loop Issued on: 04/28/1992 Inventor: Hjerpe, et al.5173617, Digital phase lock clock generator without local oscillator Issued on: 12/22/1992 Inventor: Alsup, et al.5376847Phase detector and methodology Issued on: 12/27/1994 Inventor: Staszewski International ClassH04L 007/00 |
