Efficient architecture for correcting component mismatches and circuit nonlinearities in A/D converters
Patent 5638071 Issued on June 10, 1997. Estimated Expiration Date: 
June 12, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 12, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSelf-calibrating pipelined subranging analog-to-digital converter Analog-to-digital converter with non-linear error correction Digital error correction system for subranging analog-to-digital converters Patent #: 5047772 InventorsApplicationNo. 662273 filed on 06/12/1996US Classes:341/118, CONVERTER COMPENSATION341/120CONVERTER CALIBRATION OR TESTINGExaminersPrimary: DeBoer, Todd E.Attorney, Agent or FirmInternational ClassH03M 001/06AbstractAn error correction technique for high-resolution analog-to-digital converters corrects for both component mismatch and circuit nonlinearity errors by utilizing look-up tables to store mismatch coefficients, which represent the errors introduced by component mismatch, as well as a series of offset and gain coefficients, which are utilized to form a piecewise-linear representation of the error introduced by circuit nonlinearities. The use of an independent gain and offset parameter for each segment of the piecewise-linear representation allows discontinuous functions to be accommodated. This leads to a more efficient implementation since it allows the error introduced by mismatch in the components representing the most significant bits to be included in the piecewise linear table, while separate lookup tables are used for the less significant bits.Other References
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