Avoiding instability
June 21, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesCMOS scannable latch Asynchronous signal synchronizing circuit Metastable prevent circuit Synchronizing circuit Programmable high speed state machine with sequencing capabilities Circuit for synchronizing an asynchronous input signal to a high frequency clock Non-return to zero synchronizer Asynchronous latch circuit and register Time-domain boundary bridge method and apparatus Patent #: 5418825 InventorsApplicationNo. 493383 filed on 06/21/1995US Classes:327/144, Using multiple clocks327/145, Having different frequencies327/199, Circuit having only two stable states (i.e., bistable)327/213, Plural independent clock inputs (i.e., non complementary )327/298Single clock output with multiple inputsExaminersPrimary: Callahan, Timothy P.Assistant: Lam, T. Attorney, Agent or FirmForeign Patent References
International ClassesH03K 005/00H03K 005/13 AbstractDescribed are techniques to stabilize storage devices receiving signals from plural asynchronous docks, especially to avoid "metastability", in particular, a multi-dock pulse synchronizer circuit with an IN-section for receiving and storing prescribed impulses and input cock signals, and for responsively outputting intermediate signals: and an OUT-section for receiving and storing the intermediate pulses, synchronous with certain output clock signals and processing them to generate certain output-signals which avoid metastability.Other References
Field of SearchCircuit having only two stable states (i.e., bistable)Dynamic bistable Master-slave bistable latch Using hysteresis (e.g., Schmitt trigger, etc.) Plural independent clock inputs (i.e., non complementary ) D type input Using multiple clocks Having different frequencies With feedback Synchronizing With feedforward Single clock output with multiple inputs | |
