System for processing synchronization signals with phase synchronization in mobile communication network
Patent 5636219 Issued on June 3, 1997. Estimated Expiration Date: 
February 9, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
February 9, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3725593 Digital interface for resynchronizing digital signals Distributed digital exchange with improved switching system and input processor Circuit arrangement for frame and phase synchronization of a local sampling clock Pulse insertion circuit 5117424 Drop/insert channel selecting system Circuit arrangement for clock regeneration in clock-controlled information processing systems Patent #: 5210755 InventorsAssigneeApplicationNo. 599358 filed on 02/09/1996US Classes:370/513, Plural synchronization words340/825.2, Synchronizing370/516, Adjusting for phase or jitter375/364Synchronization signals with unique amplitude, polarity, length, or frequencyExaminersPrimary: Chin, WellingtonAssistant: Vu, Huy D. Attorney, Agent or FirmForeign Patent References
International ClassH04J 003/06Foreign Application Priority Data1992-06-02 JPAbstractA system is provided for processing synchronization signals. A plurality of synchronization signals are received having different periods and different degrees of priority, and are used to generate a regenerated synchronization signal in response to clock pulses. A selector is used for selecting a selected synchronization signal, from among those received synchronization signals having a correct period. The selected synchronization signal is chosen based upon the different degrees of priority. A nonvolatile memory stores memorized synchronization signal and an allowable phase range. An address counter, which receives as an input a controllable initial value, counts the clock pulses to produce a clock count over a period of time, and to cause the nonvolatile memory to output the stored synchronization signal as a read-out synchronization signal and to output the stored allowable phase range as a read-out range, in response to the clock count. The controllable initial value, which is used as an input to the counter, is controlled by a timing control. The timing control is supplied with the selected synchronization signal from the selector and the read-out phase range from the nonvolatile memory. The timing control changes the value of the controllable initial value at such a time so as to cause the read-out synchronization signal and the read-out phase to be read from the nonvolatile memory when the selected synchronization signal has a phase in said read-out phase range.Other References
Field of SearchSYNCHRONIZERSNetwork synchronizing more than two stations Synchronization failure prevention Feedback, receiver to transmitter Self-synchronizing signal (self-clocking codes, etc.) Frequency or phase control using synchronizing signal Synchronization signals with unique amplitude, polarity, length, or frequency Synchronization word Plurality of synchronization words Synchronizer pattern recognizers With frequency detector and phase detector Phase displacement, slip or jitter correction Phase locking Synchronizing | |
