ApplicationNo. 607977 filed on 02/29/1996
US Classes:365/222, Data refresh365/195, Inhibit365/230.03, Plural blocks or banks365/233, Sync/clocking365/236Counting
ExaminersPrimary: Nelms, David C.
Assistant: Niranjan, F.
Attorney, Agent or Firm
Foreign Patent References
International ClassG11C 007/00
Foreign Application Priority Data1995-03-03 JP
AbstractA period pulse corresponding to the shortest information retention time of those of dynamic memory cells is counted to form a refresh address to be assigned to a plurality of word lines. A carry signal outputted from the refresh address counter is divided by a divider. For each of said plurality of word lines assigned with the refresh address, one of a short period corresponding to an output pulse of a timer or a long period corresponding to the divided pulse from the divider is stored in a storage circuit as refresh time setting information. A memory cell refresh operation to be performed by the refresh address is made valid or invalid for each word line according to the refresh time setting information stored in the storage circuit and the refresh time setting information itself is made invalid by the output pulse of the divider.