Method of manufacturing a buried plate type DRAM having a widened trench structure
Patent 5629226 Issued on May 13, 1997. Estimated Expiration Date: 
July 24, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 24, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor memory device Dynamic random access memory device having a plurality of improved one-transistor type memory cells Capacitor for a semiconductor Method of fibricating a semiconductor device having a trench Semiconductor memory device Patent #: 5432365 InventorApplicationNo. 506430 filed on 07/24/1995US Classes:438/389, Including doping of trench surfaces257/E21.396, Metal-insulator-semiconductor capacitor, e.g., trench capacitor (EPO)257/E21.651, Capacitor in U- or V-shaped trench in substrate (EPO)257/E27.092, Capacitor in trench (EPO)257/E27.093, Capacitor extending under or around the transistor (EPO)257/E29.343, Conductor-insulator-conductor capacitor on semiconductor substrate (EPO)257/E29.346, Trench capacitor (EPO)438/390Multiple doping stepsExaminersPrimary: Tsai, JeyAttorney, Agent or FirmForeign Patent References
International ClassesH01L 021/70H01L 027/00 Foreign Application Priority Data1992-07-13 JPAbstractA trench of a buried plate type DRAM has a bottom portion wider than an opening portion. A silicon oxide film is formed on an upper portion of the side wall of the trench. An N-type impurity diffusion region is formed around the bottom portion of the trench. Impurity diffusion regions of adjacent trenches are integrally connected with each other as one portion. A first polycrystalline silicon layer is formed on the impurity diffusion region in the trench and the silicon oxide film. The polycrystalline silicon layer is coated with a laminated film consisting of a silicon nitride film and a silicon oxide film. The trench is filled with a second polycrystalline silicon layer covering the laminated film. The impurity diffusion region serves as a plate diffusion region of a capacitor, the first polycrystalline silicon layer serves as a plate electrode, the laminated film serves as a capacitor insulating film, and the second polycrystalline silicon layer serves as a storage node electrode. The capacitor is formed in the trench.Field of SearchCapacitor in trench | |
