System for processing synchronization signals with phase synchronization in a mobile communication network
Patent 5627832 Issued on May 6, 1997. Estimated Expiration Date: 
February 9, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
February 9, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3725593 3808368 Digital interface for resynchronizing digital signals Distributed digital exchange with improved switching system and input processor Pulse insertion circuit 5117424 Drop/insert channel selecting system Circuit arrangement for clock regeneration in clock-controlled information processing systems Method and apparatus for determining equalization delays in a transmission system and related apparatus Patent #: 5327277 InventorsAssigneeApplicationNo. 598919 filed on 02/09/1996US Classes:370/508, Transmission time into time slots adjusted based upon propagation delay time375/356, Network synchronizing more than two stations375/366Plurality of synchronization wordsExaminersPrimary: Chin, WellingtonAssistant: Vu, Huy D. Attorney, Agent or FirmForeign Patent References
International ClassH04J 003/06Foreign Application Priority Data1992-06-02 JPAbstractA system for use in a local switching center is provided for processing synchronization signals. A transmission sync signal is generated at the local switching center for transmission to a switching center of a higher hierarchy for looping back to the local switching center. The looped back sync signal has a propagation delay time with respect to the transmission sync signal. A time division switch produces clock pulses. A stored pattern is read out of a non-volatile memory according to an address value provided by an address counter which counts the clock pulses of the time division switch. A delay time is also read out of the non-volatile memory according to the same address value. A phase difference signal is produced by comparing the length of the propagation delay time with the delay time read out of the non-volatile memory.Other References
Field of SearchSYNCHRONIZERSSynchronizing the sampling time of digital data Network synchronizing more than two stations Feedback, receiver to transmitter Self-synchronizing signal (self-clocking codes, etc.) Synchronization signals with unique amplitude, polarity, length, or frequency Frequency or phase control using synchronizing signal Synchronization word Synchronizer pattern recognizers Phase displacement, slip or jitter correction Plurality of synchronization words | |
