Two-level control store for microprogrammed data processor
Conditional branch unit for microprogrammed data processor
Instruction register sequence decoder for microprogrammed data processor and method
Microprocessor system with instruction pre-fetch
Data processor with parallel-operating operation units
Data processing unit utilizing data flow ordered execution
Apparatus for out-of-order program execution
Microcode control of a parallel architecture microprocessor
Microprogrammed control data processing apparatus in which operand source and/or operand destination is determined independent of microprogram control
Instruction issuing mechanism for processors with multiple functional units
ApplicationNo. 471651 filed on 06/06/1995
US Classes:712/23, Superscalar712/216, DYNAMIC INSTRUCTION DEPENDENCY CHECKING, MONITORING OR CONFLICT RESOLUTION712/239Branch prediction
ExaminersPrimary: Donaghue, Larry D.
Attorney, Agent or Firm
International ClassG06F 009/30
AbstractA processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file. The instruction fetching function operates in free-running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies. Branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later. For branches of executed instructions that are later invalidated, the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re-executed on the actual data that subsequently became available, and all subsequent instructions in such branch are also re-executed on the basis of dependencies actually available from execution of previous instructions in such branch.