U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Semiconductor device in a resin package housed in a frame having high thermal conductivity

Patent 5625222 Issued on April 29, 1997. Estimated Expiration Date: Icon_subject July 27, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Pin grid array package structure
Patent #: 4887148
Issued on: 12/12/1989
Inventor: Mu

Method of making a resin encapsulated pin grid array with integral heatsink
Patent #: 5108955
Issued on: 04/28/1992
Inventor: Ishida, et al.

Overmolded semiconductor package with anchoring means
Patent #: 5136366
Issued on: 08/04/1992
Inventor: Worp, et al.

Integral dam and heat sink for semiconductor device assembly
Patent #: 5227663
Issued on: 07/13/1993
Inventor: Patil, et al.

Pad array semiconductor device with thermal conductor and process for making the same
Patent #: 5285352
Issued on: 02/08/1994
Inventor: Pastore, et al.

Area array semiconductor device having a lid with functional contacts Patent #: 5291062
Issued on: 03/01/1994
Inventor: Higgins, III

Inventors

Application

No. 281098 filed on 07/27/1994

US Classes:

257/687, Housing or package filled with solid or liquid electrically insulating material257/700, Multiple contact layers separated from each other by insulator means and forming part of a package or housing (e.g., plural ceramic layer package)257/706, With heat sink257/713, For integrated circuit257/787, ENCAPSULATED257/E23.069, Spherical bumps on substrate for external connection, e.g., ball grid arrays (BGA) (EPO)257/E23.092, Auxiliary members in encapsulations (EPO)257/E23.102Cooling facilitated by shape of device (EPO)

Examiners

Primary: Brown, Peter R.

Attorney, Agent or Firm

Foreign Patent References

  • 0260463 JP 10/22/1990

International Classes

H01L 023/08
H01L 023/10
H01L 023/28
H01L 023/34

Foreign Application Priority Data

1993-11-18 JP

Abstract

A semiconductor device including a substrate, solder bumps provided on a lower major surface of the substrate, a semiconductor chip provided on an upper major surface of the substrate, a resin package body provided on the upper major surface of the substrate so as to bury the semiconductor chip therein, a thermally conductive frame member having a flange part supporting the substrate at a rim part of the substrate, wherein the thermal conductive frame member has a thermal conductivity substantially larger than that of the resin package body and extending along to and in an intimate contact with side walls of the resin package body.

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