MOS transistor having a composite gate electrode and method of fabrication
Patent 5625217 Issued on April 29, 1997. Estimated Expiration Date: 
February 2, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
February 2, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3576478 Method of producing titanium nitride MOS device gate electrode Composite inverse T-gate metal oxide semiconductor device and method of fabrication Patent #: 5097301 InventorsApplicationNo. 384352 filed on 02/02/1995US Classes:257/412, Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal)257/344, With lightly doped portion of drain region adjacent channel (e.g., LDD structure)257/408, Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device)257/413, Polysilicon laminated with silicide257/E21.201, Conductor layer next to insulator is Si or Ge or C and their non-Si alloys (EPO)257/E21.202, Conductor layer next to the insulator is single metal, e.g., Ta, W, Mo, Al (EPO)257/E21.203, Conductor layer next to insulator is metallic silicide (Me Si) (EPO)257/E21.204, Conductor layer next to insulator is non-MeSi composite or compound, e.g., TiN (EPO)257/E21.435, Lateral single gate single channel silicon transistor with both lightly doped source and drain extensions and source and drain self-aligned to sides of gate, e.g., LDD MOSFET, DDD MOSFET (EPO)257/E29.158, Elemental metal gate conductor material (e.g., W, Mo) (EPO)257/E29.16, Gate conductor material being compound or alloy material (e.g., organic material, TiN, MoSi 2 ) (EPO)257/E29.161, Silicide (EPO)257/E29.255With field effect produced by insulated gate (EPO)ExaminersPrimary: Loke, StevenAttorney, Agent or FirmForeign Patent References
International ClassesH01L 029/76H01L 029/94 H01L 031/062 H01L 031/113 AbstractA novel, reliable, high performance MOS transistor with a composite gate electrode which is compatible with standard CMOS fabrication processes. The composite gate electrode comprises a polysilicon layer formed on a highly conductive layer. The composite gate electrode is formed on a gate insulating layer which is formed on a silicon substrate. A pair of source/drain regions are formed in the substrate and are self-aligned to the outside edges of the composite gate electrode.Other References
Field of SearchWith lightly doped portion of drain region adjacent channel (e.g., LDD structure)With lightly doped portion of drain region adjacent channel (e.g., LDD structure) Including lightly doped drain portion adjacent channel (e.g., lightly doped drain, LDD device) Gate electrode of refractory material (e.g., polysilicon or a silicide of a refractory or platinum group metal) At least one layer of silicide or polycrystalline silicon Silicide of refractory or platinum group metal At least one layer of molybdenum, titanium, or tungsten Alloy containing molybdenum, titanium, or tungsten Molybdenum, tungsten, or titanium or their silicides Gate electrode overlaps the source or drain by no more than depth of source or drain (e.g., self-aligned gate) Gate electrode overlaps at least one of source or drain by no more than depth of source or drain (e.g., self-aligned gate) Polysilicon laminated with silicide | |
