Non-volatile memory control and data loading architecture for multiple chip processor
May 19, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSystem for processing and storing transaction data and for transmitting the transaction data to a remote host computer Centralized hardware control of multisystem access to shared and non-shared subsystems High speed program store with bootstrap Computer entry system for predetermined text data sequences Method and apparatus for programming memory through battery terminals Microcomputer with internally and externally programmed eprom Emulation with display update trapping Switching control system for multipersonality computer system Signal conditioners Security for digital signal processor program memory Inventors
ApplicationNo. 446079 filed on 05/19/1995US Classes:712/32Microprocessor or multichip or multimodule processor having sequential program controlExaminersPrimary: Shah, Alpesh M.Attorney, Agent or FirmInternational ClassG06F 015/76AbstractAn architecture for a serial multi-chip package digital controller including a controller oriented processor die and a separate non-volatile memory die. The architecture provides for a low pin count on the package, minimal electrical connections on and between the dice, and a minimal number of registers by making use of significant multiplexing to allow many of the registers and signal lines to serve multiple functions responsive to the mode of operation and other control signals.An input data register on the non-volatile memory die and a related multiplexer allows data from different sources to be loaded into the input data register depending on the mode of operation. Also, the output of the input data register is coupled to plural locations so that the destination of the data can also be switched responsive to the mode of operation. Particularly, the output of the input data register is coupled to an output port, a program data register (through which program data can be loaded into the program memory), and a control register for setting various control bits for performing specific integrity tests which can be performed following fabrication. Accordingly, the input data register is used for programming the memory from an external source, setting control bits from an external device, and sending data from the processor to the R port and on to external devices.Other References
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