Apparatus for maintaining coherency of cache memory data
October 14, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesApparatus and method for detecting and handling memory-mapped I/O by a pipelined microprocessor Cache which provides status information Interface between buses attached with cached modules providing address space mapped cache coherent memory access with SNOOP hit memory updates Methods and apparatus for caching interlock variables in an integrated cache memory Apparatus and method for reducing interference in two-level cache memories System and method for processor pipeline control by selective signal deassertion Apparatus and method for a synchronous, high speed, packet-switched bus Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes Patent #: 5214767 InventorApplicationNo. 323501 filed on 10/14/1994US Classes:711/141, Coherency711/146SnoopingExaminersPrimary: Treat, William M.Attorney, Agent or FirmInternational ClassG06F 012/00Foreign Application Priority Data1990-08-08 JPAbstractA data processor for maintaining coherency of data in a cache memory. The processor includes two memory-data-coherency maintaining devices and an operation mode changing device for changing a combination of operation modes of the maintaining devices, thereby enabling one kind of data processor to be adaptable to a plurality of different system structures and optimum memory-data-coherency to be maintained.Other References
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