Patent ReferencesSemiconductor memory device having a bit line constituted by a semiconductor layer Method of forming high-dielectric-constant material electrodes comprising sidewall spacers Pre-oxidizing high-dielectric-constant material electrodes Patent #: 5554866 InventorApplicationNo. 620209 filed on 03/22/1996US Classes:365/145, Ferroelectric257/295, With ferroelectric material layer257/310, With high dielectric constant insulator (e.g., Ta 2 O 5 )257/768, Refractory or platinum group metal or alloy or silicide thereof257/769, Platinum group metal or silicide thereof257/915, WITH TITANIUM NITRIDE PORTION OR REGION257/E27.104, Ferroelectric non-volatile memory structure (EPO)257/E29.272Gate comprising ferroelectric layer (EPO)ExaminersPrimary: Nelms, David C.Assistant: Le, Vu A. International ClassH01L 027/108Foreign Application Priority Data1995-03-22 KRAbstractA ferroelectric memory device of an MFIS FET structure using a yttrium oxide film as a buffer film and a manufacturing method of the memory device are provided. The MFIS FET includes a p-type silicon substrate, a field oxide film formed in a device isolation region of the silicon substrate, a gate yttrium oxide film formed on the surface of the silicon substrate, a gate ferroelectric film formed on the gate yttrium oxide film, a gate TiN electrode formed on the gate ferroelectric film, and an n-type source/drain region formed in the silicon substrate of both sides of the gate TiN electrode. In this way, single crystals of the gate yttrium oxide film are easily formed resulting in the formation of a good-quality ferroelectric film on the yttrium oxide film.Field of SearchFerroelectricCapacitors With ferroelectric material layer With high dielectric constant insulator (e.g., Ta 2 O 5 ) Refractory or platinum group metal or alloy or silicide thereof Platinum group metal or silicide thereof WITH TITANIUM NITRIDE PORTION OR REGION Insulated gate capacitor or insulated gate transistor combined with capacitor (e.g., dynamic memory cell) | |