Method and apparatus for the transparent emulation of an existing instruction-set architecture by an arbitrary underlying instruction-set architecture
April 13, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMacroinstruction translator unit for use in a microprocessor Microprocessor memory management and protection mechanism Extended floating point operations supporting emulation of source instruction execution Translating a dynamic transfer control instruction address in a simulated CPU processor Memory mapping and special write detection in a system and method for simulating a CPU processor Address selective emulation routine pointer address mapping system Patent #: 5392408 InventorAssigneeApplicationNo. 421344 filed on 04/13/1995US Classes:712/208, INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED)703/26, Of instruction703/27Compatibility emulationExaminersPrimary: Treat, William M.Assistant: Assefa, Amare Attorney, Agent or FirmForeign Patent References
International ClassG06F 009/455AbstractThe invention provides means and methods for extending an instruction-set architecture without impacting the software interface. This circumvents all software compatibility issues, and allows legacy software to benefit from new architectural extensions without recompilation and reassembly. The means employed are a translation engine for translating sequences of old architecture instructions into primary, new architecture instructions, and an extended instruction (EI) cache memory for storing the translations. A processor requesting a sequence of instructions will look first to the EI-cache for a translation, and if translations are unavailable, will look to a conventional cache memory for the sequence, and finally, if still unavailable, will look to a main memory.Other References
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