Patent ReferencesPipelined digital processor arranged for conditional operation Series maxium/minimum function computing devices, systems and methods Branch control in a three phase pipelined signal processor Branch address calculating system for branch instructions Digital signal processor with conditional branch decision unit and storage of conditional branch decision results Digital data processor executing a conditional instruction within a single machine cycle Computer system with clock shared between processors executing separate instruction streams Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts Patent #: 5442757 InventorsAssigneeApplicationNo. 288539 filed on 08/10/1994US Classes:712/200, ARCHITECTURE BASED INSTRUCTION PROCESSING712/32Microprocessor or multichip or multimodule processor having sequential program controlExaminersPrimary: Auve, Glenn A.Attorney, Agent or FirmInternational ClassG06F 009/30AbstractA data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed. | |