U.S. patents available from 1976 to present.
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Devices, systems and methods for conditional instructions

Patent 5617574 Issued on April 1, 1997. Estimated Expiration Date: Icon_subject August 10, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Pipelined digital processor arranged for conditional operation
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Series maxium/minimum function computing devices, systems and methods
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Branch control in a three phase pipelined signal processor
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Issued on: 01/14/1992
Inventor: Larsen, et al.

Branch address calculating system for branch instructions
Patent #: 5088030
Issued on: 02/11/1992
Inventor: Yoshida

Digital signal processor with conditional branch decision unit and storage of conditional branch decision results
Patent #: 5247627
Issued on: 09/21/1993
Inventor: Murakami, et al.

Digital data processor executing a conditional instruction within a single machine cycle
Patent #: 5274777
Issued on: 12/28/1993
Inventor: Kawata

Computer system with clock shared between processors executing separate instruction streams
Patent #: 5428754
Issued on: 06/27/1995
Inventor: Baldwin

Computer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interrupts Patent #: 5442757
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Inventor: McFarland, et al.

Inventors

Assignee

Application

No. 288539 filed on 08/10/1994

US Classes:

712/200, ARCHITECTURE BASED INSTRUCTION PROCESSING712/32Microprocessor or multichip or multimodule processor having sequential program control

Examiners

Primary: Auve, Glenn A.

Attorney, Agent or Firm

International Class

G06F 009/30

Abstract

A data processing device includes a circuit having status conditions wherein a particular set of the status conditions can occur in operation of the circuit. An instruction register operates to hold a branch instruction conditional on a particular set of the status conditions. A decoder is connected to the instruction register and the circuit. A program counter is coupled to the decoder wherein the decoder is operable to enter a branch address into the program counter in response to the branch instruction when the particular set of the status conditions of the circuit are present. Other data processing devices, systems and methods are also disclosed.

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