Data Processor having a built-in internal self test controller for testing a plurality of memories internal to the data processor
July 10, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSelf-testing pipeline processors Self diagnostic Cyclic Analysis Testing System (CATS) for LSI/VLSI Semiconductor integrated circuit device with built-in arrangement for memory testing Value-strength based test pattern generator and process Method and apparatus for testing circuit boards Structured scan path circuit for incorporating domino logic System for scan testing of logic circuit networks System scan path architecture with remote bus controller Built-in test circuit for static CMOS circuits Built-in self-test technique for content-addressable memories InventorsAssigneeApplicationNo. 500271 filed on 07/10/1995US Classes:714/30, Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path)714/5, Of memory or peripheral subsystem714/10, Of processor714/744, Clock or synchronization714/763Memory accessExaminersPrimary: Beausoliel, Robert W. Jr.Assistant: Le, Dieu-Minh Attorney, Agent or FirmInternational ClassG06F 011/08AbstractA data processor (10) has a single test controller (11). The test controller (11) has a test pattern generator portion (26) and a memory verification element (27). The test pattern generator (26) generates and communicates a plurality of test patterns to the plurality of memories (12, 13, and 14) through a second storage device (17). A first storage device (16) is used to store data read from the plurality of memories (12, 13, and 14). The data from the first storage device is selectively accessed by the memory verification element (27) via the bus (31). A bit (32) or more than one bit is used to communicate to external to the processor (10) whether the memories (12, 13, and 14) are operating in an error free manner.Other References
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