System having independently addressable bus interfaces coupled to serially connected multi-ported signal distributors generating and maintaining frame based polling schedule favoring isochronous peripherals

Patent 5615404 Issued on March 25, 1997. Estimated Expiration Date:

October 31, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Abstract Claims Description Full Text

Patent References

3245045

3916387

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Inventors

Application

No. 332255 filed on 10/31/1994

US Classes:

710/62, Peripheral adapting710/3, Input/Output addressing710/44, Prioritized polling710/110, Bus master/slave controlling711/211Address multiplexing or address bus manipulation

Examiners

Primary: Lee, Thomas C.
Assistant: Nahm, Sang Y.

Attorney, Agent or Firm

Blakely, Sokoloff, Taylor & Zafman

International Class

G06F 013/12

Abstract

A bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces are provided for form an hierarchical serial bus assembly for serially interfacing a number of isochronous and asynchronous peripherals to the system unit of a computer system. The bus controller, bus signal distributors, and bus interfaces are provided with circuitry and complementary logic for implementing a master/slave model of flow control for serially interfacing the bus agents to each other to conduct data communication transactions. In certain embodiments, these circuitry and complementary logic further conduct connection management transactions employing also the master/slave model of flow control, implement a frame based polling schedule for polling the slave "devices", employ at least two address spaces to conduct the various transactions, support communication packet based transactions, and/or electrically represent data and/or control states.

Other References

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