Semiconductor memory device having a plurality of writing and reading ports for decreasing hardware amount
Four port RAM cell
Multi-port static random access memory with fast write-thru scheme Patent #: 5473574
ApplicationNo. 644081 filed on 05/09/1996
US Classes:365/230.05, Multiple port access365/230.06, Particular decoder or driver circuit365/233Sync/clocking
ExaminersPrimary: Nelms, David C.
Assistant: Hoang, Huan
Attorney, Agent or Firm
International ClassG11C 008/00
AbstractDisclosed is a design detail for an innovative time multiplexed read port architecture implemented as part of a high-speed 9-port time slot interchange random access memory. It provides a practical, high-speed, low-power and area efficient read port structure to allow eight random access reads per clock cycle. Because all timing is internally generated from a single rising clock transition of a system clock signal, no special control or clocking is required externally to the memory.