Bus architecture for digital signal processor allowing time multiplexed access to memory banks
Patent 5611075 Issued on March 11, 1997. Estimated Expiration Date: 
July 29, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
July 29, 2016. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMultiple microprocessor intercommunication arrangement Dynamically programmable processing element Remote I/O port for transfer of I/O data in a programmable controller Network communications adapter with dual interleaved memory banks servicing multiple processors Time sliced vector processing Abdominal exercise device Hybrid multiplex synchronizing method and apparatus therefor Method and apparatus for accessing variable length words in a memory array Patent #: 5396608 InventorAssigneeApplicationNo. 681905 filed on 07/29/1996US Classes:711/153Shared memory partitioningExaminersPrimary: Coleman, EricAttorney, Agent or FirmForeign Patent References
International ClassG06F 013/00AbstractA monolithic digital signal processor includes a core processor for performing digital signal computations, an I/O processor for controlling external access to and from the digital signal processor through an external port, first and second memory banks for storing instructions and data for the digital signal computations, and first and second buses interconnecting the core processor, the I/O processor and the memory banks. The core processor and the I/O processor access the memory banks on the first bus without interference on different clock phases of a clock cycle. The internal memory and the I/O processor of the digital signal processor are assigned to a region of a global memory space, which facilitates multiprocessing configurations. In a multiprocessor system, each digital signal processor is assigned a processor ID. The digital signal processor includes a bus arbitration circuit for controlling access to an external bus through the external port. The digital signal processor may include one or more serial ports and one or more link ports for point-to-point communication with external devices. A DMA controller controls DMA transfers through the external port, the serial ports and the link ports.Other References
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