U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Method and apparatus for multiplexing signals from a bus bridge to an ISA bus interface and an ATA bus interface

Patent 5606672 Issued on February 25, 1997. Estimated Expiration Date: Icon_subject January 27, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Node controller for a local area network
Patent #: 5043938
Issued on: 08/27/1991
Inventor: Ebersole

Logic support chip for AT-type computer with improved bus architecture
Patent #: 5125080
Issued on: 06/23/1992
Inventor: Pleva, et al.

Local bus design
Patent #: 5309568
Issued on: 05/03/1994
Inventor: Ghosh, et al.

Dual bus interface transfer system for central processing module
Patent #: 5404462
Issued on: 04/04/1995
Inventor: Datwyler, et al.

Bus-to-bus bridge for a multiple bus information handling system that optimizes data transfers between a system bus and a peripheral bus Patent #: 5499346
Issued on: 03/12/1996
Inventor: Amini, et al.

Inventor

Application

No. 380020 filed on 01/27/1995

US Classes:

710/316, Path selecting switch710/306Bus bridge

Examiners

Primary: Harvey, Jack B.
Assistant: Lefkowitz, Sumati

Attorney, Agent or Firm

International Class

G06F 013/00

Abstract

An apparatus and method for connecting a bus bridge to a plurality of bus interfaces. The invention allows output lines on a bus bridge to be shared so that a minimal amount of dedicated pins are utilized. Signals on the bus bridge which need to be driven and received quickly are connected directly from the bus bridge to the bus interfaces. Signals on the bus bridge which do not need to be driven and received quickly are connected from the bus bridge to the bus interfaces though buffers. The invention allows the bus bridge to interface a high speed local bus and a plurality of I/O buses while satisfying the timing requirements of each of the I/O buses.

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