U.S. patents available from 1976 to present.
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Emulation system employing motherboard and flexible daughterboards

Patent 5604888 Issued on February 18, 1997. Estimated Expiration Date: Icon_subject April 7, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

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Method and apparatus for debugging reconfigurable emulation systems
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Inventors

Assignee

Application

No. 224148 filed on 04/07/1994

US Classes:

703/23, EMULATION714/725, Programmable logic array (PLA) testing714/734Structural (in-circuit test)

Examiners

Primary: Teska, Kevin J.
Assistant: Nguyen, Tan T.

Attorney, Agent or Firm

Foreign Patent References

  • 2179372 GB. 05/19/1987

International Classes

G06F 017/00
G06F 013/00

Abstract

The use of daughterboards connecting to a motherboard in an emulation system allows for the upgrading of the emulation field programmable gate arrays in the system, and for the use of different types of field programmable gate arrays. These changes can be made without changing the motherboard. The motherboard has sockets which have pin locations which are allocated to interconnect structures and to an emulation bus. The chips on the cards can contain different emulation field programmable gate arrays, or could contain core chips, which can be directly connected to the motherboard through the daughterboards. The daughterboards connect the emulation FPGAs and the core chips to the correct pin locations of the sockets. Controller chips on the cards allow for different types of field programmable gate arrays to be used and simplify the configuration loading and debugging of the system. Additionally, the present system includes a system using a reconfigurable interface in a controller chip. This reconfigurable interface allows for different types of field programmable gate arrays to be used in the emulation system.

Other References

  • Lee et al., "The Motorola 16-Bil DSP ASIC Core", IEEE 1990, pp. 973-976
  • Hasslen et al., "A Validation Strategy for Embedded Core ACIC" IEEE 1990, pp. P5-31-to P5-32
  • Pasternak et al., "In-Circuit-Emulation in ASIC Architecture Core Designs", IEEE 1989, pp. P6-4.1 to P6-4.4
  • Breuer, Melvin A., ed.; Design Automation of Digital Systems, vol. One; Chapter 4, "Partitioning and Card Selection"; Prentice-Hall, Inc.; date unknown; pp. 173-212
  • The Programmable Gate Array Design Handbook, First Edition; Xilinx, San Jose, California; 1986
  • Proceedings of the IEEE; Jul., 1993; pp. 1011-108
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