Channel-stop process for use with thick-field isolation regions in triple-well structures
October 25, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor wafer processing method of forming channel stops and method of forming SRAM circuitry Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods Method of forming a floating gate programmable read only memory cell transistor Method of fabricating a semiconductor device having a triple well structure Method for forming a high density EEPROM cell array with improved access time Patent #: 5453393 InventorAssigneeApplicationNo. 547852 filed on 10/25/1995US Classes:438/257, Having additional gate electrode surrounded by dielectric (i.e., floating gate)257/E21.545, Dielectric regions, e.g., EPIC dielectric isolation, LOCOS; trench refilling techniques, SOI technology, use of channel stoppers (EPO)438/201, Including insulated gate field effect transistor having gate surrounded by dielectric (i.e., floating gate)438/258, Including additional field effect transistor (e.g., sense or access transistor, etc.)438/450Implanting through recessed oxideExaminersPrimary: Dang, TrungAttorney, Agent or FirmInternational ClassH01L 021/76AbstractTo ensure proper electrical insulation under thick-field isolation regions (23) grown in triple-well structures, the channel-stop impurity (30) is implanted using multiple doses at different energies, depending on the oxide thickness of the thick-field isolation regions (23). The split-implant procedure results in much wider process variation windows for the thick-field isolation regions (23). Process variations include oxide thickness of grown oxide, implant energy/dose and reduced thickness caused by wet de-glazing steps. | |
