CMOS full adder circuit with pair of carry signal lines
Patent 5596520 Issued on January 21, 1997. Estimated Expiration Date: 
October 4, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
October 4, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesRipple-carry generating circuit with carry regeneration MOS transistor circuit Manchester type carry propagation circuit Parallel binary adder having grouped stages including dynamic logic to increase carry propagation speed Patent #: 4858167 InventorsAssigneeApplicationNo. 317435 filed on 10/04/1994US Classes:708/707, Carry-ripple708/702, Field-Effect transistor (FET)708/704For precharging (e.g., Manchester, etc.)ExaminersPrimary: Mai, Tan V.Attorney, Agent or FirmForeign Patent References
International ClassG06F 007/50Foreign Application Priority Data1993-10-04 JPAbstractA full adder circuit has a plurality of full adders each provided for each bit. Each full adder has: a calculation block (31a) responsive to a first carry signal (C) given by a preceding stage bit as a differential signal and two external input data (A1, B1) to be added at a present stage bit, for outputting addition data calculated on the basis of the first carry signal and the external input data as two differential signals, and further outputting a second carry signal (/C) to a succeeding bit as a differential signal indicative of whether a carry is generated by the present stage bit or not. Each full adder also has a latch type sense amplifier (16a) for outputting an addition result (SUM) of the present stage bit, after having differentially amplified and latched the addition data outputted by the calculation block. Since the addition operation is made on the basis of the carry signals (C and /C) of a minute potential difference (before amplification), it is possible to shorten the required charging time and to reduce the current consumption. In addition, since the sense amplifiers (16a) are provided with the latch function (18a), it is possible to control the differential amplification operation and the latch operation on the basis of a common sense amplifier activating signal (SAB), so that the number of elements can be reduced. | |
