Method and apparatus for unobtrusively monitoring processor states and characterizing bottlenecks in a pipelined processor executing grouped instructions
Patent 5594864 Issued on January 14, 1997. Estimated Expiration Date: 
May 30, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
May 30, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesData processing system with a pipelined structure for editing trace memory contents and tracing operations during system debugging High speed microcomputer in-circuit emulator Patent #: 5321828 InventorApplicationNo. 454406 filed on 05/30/1995US Classes:714/39, Monitor recognizes sequence of events (e.g., protocol or logic state analyzer)712/227, Specialized instruction processing in support of testing, debugging, emulation714/30, Built-in hardware for diagnosing or testing within-system component (e.g., microprocessor test mode circuit, scan path)714/31, Additional processor for in-system fault locating (e.g., distributed diagnosis program)714/38Of computer softwareExaminersPrimary: Treat, William M.Attorney, Agent or FirmInternational ClassesG06F 011/25G06F 011/34 AbstractMethods and apparatus are presented for unobtrusively monitoring processor states and characterizing bottlenecks in an arbitrary customer workload. An instruction queue and an instruction control unit within a pipelined central processor unit (CPU) provide for grouping and issuing multiple instructions per clock cycle for overlapped execution. Additionally, instruction and data caches in operation with integer and floating point function units issue a program counter to the instruction cache, which subsequently supplies instructions to integer and floating point instruction queues. Both integer and floating point unit datapaths comprise fetch, decode, execute, and writeback stages. In the preferred embodiment, ten additional datalines transmitting PIPE signals are routed from the integer and floating point function units to contact pins on an external pin gate array supporting the CPU. The ten PIPE signals provide information on activity of key internal states of the pipelined processor within a single clock cycle. The PIPE signals may be monitored by a logic analyzer, thereby forming an external hardware monitor. By tracing the ten PIPE signals, the number of instructions issued in each stall-free cycle and total number of cycles elapsed may be determined, permitting determination of bottlenecks in customer software on the target CPU, as well as yielding information for optimizing the CPU to execute customer software more efficiently. Based on the accumulated and tabulated performance data, a CPU vendor can reconfigure hardware and/or software to more precisely meet customer workload needs based on determination of customer software operating in the customers actual work environment.Other References
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