Apparatus and method for distributed control in a processor architecture
Patent 5592679 Issued on January 7, 1997. Estimated Expiration Date: 
November 14, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
November 14, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 4594660 Superscalar processor having bypass circuit for directly transferring result of instruction execution between pipelines without being written to register file Idiom recognizer within a register alias table Apparatus and method for renaming registers in a processor and resolving data dependencies thereof Patent #: 5524262 InventorApplicationNo. 339518 filed on 11/14/1994US Classes:712/23, Superscalar711/117, Hierarchical memories712/219Reducing an impact of a stall or pipeline bubbleExaminersPrimary: Donaghue, Larry D.Attorney, Agent or FirmInternational ClassG06F 015/82AbstractThe present invention provides a multi-level instruction scheduling system for controlling multiple execution pipes of a distributed data flow (DDF) processor. The multi-level scheduling system includes a simple global instruction scheduler and multiple local instruction schedulers corresponding to the number of execution pipes. The global instruction scheduler is responsible for distributing instructions among the execution pipes. Each local instruction scheduler is only responsible for scheduling its share of distributed instructions and matching the reduced number of instructions with the execution units of the corresponding execution pipe when all its source operands are available. Source operands are garnered in one of three ways. First, the local instruction scheduler ensures that locally generated register operand values are stored in a local register buffer and made available quickly to younger instructions distributed to the execution pipe. Second, when source operand values of the instruction are not available in the local register buffer, an inter-pipe operand request is made to an arbiter. If the operand value(s) is available from another execution pipe, a transfer of the source operand(s) is initiated via an inter-pipe bypass coupling the first and second execution pipes. Third, if the source register operand value(s) cannot be found in any of the other execution pipes, the register operand value(s) is retrieved from a global register file via an inter-pipe bypass. This multiple execution pipe architecture advantageously lends itself to software optimizing techniques such as multi-tasking, system exception/trap handling and speculative execution, e.g., instruction branch prediction techniques.Other References
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