Memory access method and apparatus in multiple processor systems
Nonvolatile memory unlock for an electronic postage meter
Program/erase selection for flash memory
Apparatus for providing block erasing in a flash EPROM
Burst EPROM architecture
Synchronizing and processing of memory access operations in multiprocessor systems using a directory of lock bits
Memory device with a test mode
Processor controlled command port architecture for flash memory
Apparatus for determining the conditions of programming circuitry used with flash EEPROM memory
Row redundancy for flash memories
ApplicationNo. 085546 filed on 06/30/1993
US Classes:711/103, Programmable read only memory (PROM, EEPROM, etc.)365/185.04, Data security365/185.11, Bank or block architecture365/195, Inhibit711/152, Memory access blocking711/156, Status storage711/163Access limiting
ExaminersPrimary: Chan, Eddie P.
Assistant: Bragdon, Reginald G.
Attorney, Agent or Firm
Foreign Patent References
International ClassG06F 012/14
AbstractA method and device for selectively enabling and disabling write access to flash blocks in a flash memory device. A lock command locks and unlocks a flash block in a flash array containing a plurality of flash blocks. A block data row decoder selects a block data area of the flash block, and a block status row decoder selects a block status area of the flash block. A lock bit in the block status area is programmed to a first logic state if the lock command specifies a lock flash block operation, or to a second logic state if the lock command specifies a release flash block operation. If a write protect input, read from the write protect pin of the flash memory device, indicates that a write lock is enabled and if a block enabled status bit in a block status register corresponding to the block indicates that the block has the write lock, then the lock bit is read and stored into the block enabled status bit in the block status register corresponding to the block. The write protect input is read again from the write protect pin and if the write protect input indicates that the write lock is enabled, and if the block enabled status bit in the block status register corresponding to the block, as updated, indicates that the block has the write lock, then an error is signaled.