Parallel processing data network of master and slave transputers controlled by a serial control network
September 26, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDigital bus and control circuitry for data routing and transmission Interface apparatus for coupling a minicomputer to a microcomputer for the transfer of data between them and method for using same Parallel computer Multiple task oriented processor Remote multiplexer terminal with redundant central processor units Multiprocessor system employing dynamically programmable processing elements controlled by a master processor Delta network of a cross-point switch Binary data compression and expansion processing apparatus A plurality of optical crossbar switches and exchange switches for parallel processor computer Method and apparatus for transmission of digital data InventorAssigneeApplicationNo. 312435 filed on 09/26/1994US Classes:712/29, Interface710/104, System configuring712/31Master/slaveExaminersPrimary: Barry, Lance LeonardAttorney, Agent or FirmForeign Patent References
International ClassG06F 015/16AbstractThe present device provides for a dynamically configurable communication network having a multi-processor parallel processing system having a serial communication network and a high speed parallel communication network. The serial communication network is used to disseminate commands from a master processor (100) to a plurality of slave processors (200) to effect communication protocol, to control transmission of high density data among nodes and to monitor each slave processor's status. The high speed parallel processing network is used to effect the transmission of high density data among nodes in the parallel processing system. Each node comprises a transputer (104), a digital signal processor (114), a parallel transfer controller (106), and two three-port memory devices. A communication switch (108) within each node (100) connects it to a fast parallel hardware channel (70) through which all high density data arrives or leaves the node.Other References
Field of SearchAdaptive coding | |
