Circuits systems and methods for reducing power loss during transfer of data across a conductive line
October 13, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3906254 Level shift circuit Speed up circuit Monolithic CMOS low power digital level shifter Input signal conditioning circuit CMOS output circuit device Latch circuit for a programmable logic device using dual n-type transistors Ultra fast logic CMOS digital level shifter circuit Drivers and receivers for interfacing VLSI CMOS circuits to transmission lines InventorsAssigneeApplicationNo. 543210 filed on 10/13/1995US Classes:326/86, Bus driving326/21, SIGNAL SENSITIVITY OR TRANSMISSION INTEGRITY326/81CMOSExaminersPrimary: Hudspeth, DavidAttorney, Agent or FirmInternational ClassH03K 019/017.5AbstractA line driver 202 is provided for transmitting signals across a line 201. Line driver 202 receives an input signal having a first voltage swing between a first high voltage level and a first low voltage level. Line driver 202 reduces power dissipation in line 201 by transmitting an output signal on line 201 having a second voltage swing between a second low voltage level greater than the first low voltage level and a second high voltage level less than the first high voltage level. | |
