Direct memory access control device and method in a multiprocessor system accessing local and shared memory
December 19, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesDirect memory access data transfer system for use with plural processors Modular computer system Data transmitting link High speed parallel bus and data transfer method Modular computer system Display control apparatus for controlling to write image data to a plurality of memory planes Process and circuit arrangement for addressing the memories of a plurality of data processing units in a multiple line system Multizone array processor implementing two sided zone buffers with each side being dynamically configured as a working or I/O side Architecture for a distributive microprocessing system Break points system in a software monitor where entry address of break point routing equals op code of call instruction InventorsApplicationNo. 358670 filed on 12/19/1994US Classes:711/117, Hierarchical memories710/107, Bus access regulation710/308, Direct memory access (e.g., DMA)711/121, Private caches711/147Shared memory areaExaminersPrimary: Swann, Tod R.Assistant: Peikari, B. James Attorney, Agent or FirmInternational ClassesG06F 013/40G06F 013/36 G06F 012/08 Foreign Application Priority Data1988-11-25 JPAbstractA direct memory access control device is used in a multiprocessor system having a plurality of digital data processors and an external common memory connected in common to those digital data processors through a first bus. In the case of transferring data in a direct memory access mode between processors, the transfer of data between the processors is effected by the control device through a second data bus provided in common to the plurality of digital data processors separately from the first bus. Thus, data can be transferred directly in a direct memory access mode between the processors without using the external memory and high-speed transfer can be realized. In addition, the control device comprises registers for storing the status bits of each digital data processor, such as direct memory access request and acceptance signals, corresponding to each digital data processor. Request and acceptance of direct memory access and transfer of data are effected by monitoring the contents of those registers.Other References
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