Semiconductor integrated circuit device having power reduction mechanism
February 8, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSemiconductor integrated circuit with a response time compensated with respect to temperature Current-mirror-biased pre-charged logic circuit MOS no-leak circuit Two-mode driver circuit Semiconductor circuit with low power consumption having emitter-coupled logic or differential amplifier Output buffer circuits for reducing noise CMOS type input buffer circuit for semiconductor device and semiconductor device with the same Low power CMOS bus receiver with small setup time CMOS buffer circuit which is not influenced by bounce noise CMOS clocked logic decoder InventorsAssigneeApplicationNo. 193765 filed on 02/08/1994US Classes:326/121, CMOS326/17, ACCELERATING SWITCHING326/33, Bias or power supply level stabilization326/83, Field-effect transistor327/544Power conservation or pulse typeExaminersPrimary: Westin, Edward P.Assistant: Santamauro, Jon Attorney, Agent or FirmForeign Patent References
International ClassesH03K 019/094.8H03K 019/01 Foreign Application Priority Data1992-04-14 JPAbstractA semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.Other References
Field of SearchMOSFET (i.e., metal-oxide semiconductor field-effect transistor)Depletion or enhancement CMOS ACCELERATING SWITCHING Signal level or switching threshold stabilization Bias or power supply level stabilization CMOS Field-effect transistor Power conservation or pulse type With field-effect transistor | |
