U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Inverter gate circuit of a bi-CMOS structure having common layers between fets and bipolar transistors

Patent 5583363 Issued on December 10, 1996. Estimated Expiration Date: Icon_subject December 10, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Circuit combining bipolar transistor and JFET's to produce a constant voltage characteristic
Patent #: 4066917
Issued on: 01/03/1978
Inventor: Compton ,   et al.

Method of making MIS field effect transistor having a lightly-doped region
Patent #: 4597827
Issued on: 07/01/1986
Inventor: Nishitani ,   et al.

Fabrication of a semiconductor device containing deep emitter and another transistor with shallow doped region
Patent #: 4783423
Issued on: 11/08/1988
Inventor: Yamauchi

Protection system for CMOS integrated circuits
Patent #: 4819047
Issued on: 04/04/1989
Inventor: Gilfeather ,   et al.

Power feeding and input signal switching control system for video tape recorder combined with television receiver and camera in a body Patent #: 4862290
Issued on: 08/29/1989
Inventor: Jung ,   et al.

Inventors

Assignee

Application

No. 860596 filed on 03/30/1992

US Classes:

257/378, Combined with bipolar transistor257/370, Combined with bipolar transistor257/E27.031In combination with vertical bipolar transistor and diode, capacitor, or resistor (EPO)

Examiners

Primary: Meier, Stephen D.

Attorney, Agent or Firm

Foreign Patent References

  • 0226892 EP 01/20/1987
  • 0310797 EP 12/20/1989
  • 266212 DD. 03/20/1989
  • 47-18482 JP. 09/20/1972
  • 50-261181 JP. 08/20/1975
  • 52-26181 JP. 08/20/1975
  • 56-152260 JP. 11/20/1981
  • 62-174965 JP. 07/20/1987
  • 62-200757 JP 09/20/1987
  • 62-293665 JP. 12/20/1987
  • 63-244767 JP. 12/20/1988
  • 8300407 WO. 02/20/1983

International Classes

H01L 029/76
H01L 029/94
H01L 031/062
H01L 031/113

Foreign Application Priority Data

1989-01-30 JP

Abstract

A semiconductor device comprises a p-type semiconductor substrate, an n-type semiconductor well formed on the substrate and connected to a positive power supply, a p-type semiconductor source formed within the n-type semiconductor well, a p-type semiconductor layer formed within the n-type semiconductor well and having a lower impurity concentration than the p-type semiconductor source, a first gate electrode formed over a region between the p-type semiconductor source and the p-type semiconductor layer through an insulating film, an n-type semiconductor emitter formed over the p-type semiconductor layer within the n-type semiconductor well, a first conductive layer formed over the n-type semiconductor well to connect with said p-type semiconductor source.

Other References

  • Muller et al, Device Electronics for IC's, pp. 301-303, 1986
  • Gaensslen et al, Hybrid IgFET--Bipolar Transistor IBM Tech, vol. 12, #12, 1970, pp. 2327-2328
  • Japanese Patent Abstracts, vol. 11, No. 384, Dec. 15, 1987 & JP-A-62 150 760 Jul. 4, 1987
  • Japanese Patent Abstracts, vol. 10, No. 170, Jun. 1986 & JP-A-61 020 425 Jan. 29, 1986
  • Japanese Patent Abstracts, vol. 12, No. 9, Jan. 12, 1988 & JP-A-62 169 466 Jul. 25, 1987
  • IBM Techinal Disclosure Bulitin. vol. 28, No. 8, Jan. 1986, pp. 3558-3561
  • Neues Aus Der Technik, No. 2, Apr. 1, 1977 `Speicher Mit Magnetishchen "Bubble-Domanan"`, col. 3; figure 5
  • "Full-Swing Complementary BiCMOS Logic Circuits", Hyn J. Shin, et al. Proceedings of the 1989 Bipolar Circuits and Technology Meeting IEEE, 89CH2771-4 Paper 8.7 pp. 229-23
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