Patent ReferencesCompiling method for vectorizing multiple do-loops in source program Method for converting an iterative loop of a source program into parellelly executable object program portions Parallelization compile method and system Processor scheduling method for iterative loops Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip System for compiling iterated loops based on the possibility of parallel execution Patent #: 5317743 InventorAssigneeApplicationNo. 395373 filed on 02/21/1995US Classes:712/241Loop executionExaminersPrimary: Eng, David Y.Attorney, Agent or FirmForeign Patent References
International ClassG06F 009/45Foreign Application Priority Data1991-11-11 JPAbstractThe present invention provides an apparatus for detecting possibility to process in parallel a program including a loop where iteration processing is executed comprising a simulation unit for simulating each iteration of the loop in the program, a variable storage unit for storing information based on the simulation as to a variable whose value is defined in a program statement in relation with information showing a location where in the program the value of the variable is defined, and a judgement unit for judging whether or not parallel processing is possible by referring to the variable storage unit for information of the location;The present invention further provides a program translation apparatus for generating a program applicable to parallel processing based on the detected possibility of executing the program in parallel comprising the simulation unit, the variable storage unit, the judgement unit, and the program generation means for generating the program applicable to parallel processing when it is judged by the judgement unit that parallel processing of the program is possible.Other References
| |