U.S. patents available from 1976 to present.
U.S. patent applications available from 2005 to present.

Apparatus for detecting possibility of parallel processing and method thereof and a program translation apparatus utilized therein

Patent 5579494 Issued on November 26, 1996. Estimated Expiration Date: Icon_subject February 21, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.

Patent References

Compiling method for vectorizing multiple do-loops in source program
Patent #: 4833606
Issued on: 05/23/1989
Inventor: Iwasawa ,   et al.

Method for converting an iterative loop of a source program into parellelly executable object program portions
Patent #: 5067068
Issued on: 11/19/1991
Inventor: Iwasawa, et al.

Parallelization compile method and system
Patent #: 5151991
Issued on: 09/29/1992
Inventor: Iwasawa, et al.

Processor scheduling method for iterative loops
Patent #: 5230053
Issued on: 07/20/1993
Inventor: Zaiki

Scan mechanism for monitoring the state of internal signals of a VLSI microprocessor chip
Patent #: 5253255
Issued on: 10/12/1993
Inventor: Carbine

System for compiling iterated loops based on the possibility of parallel execution Patent #: 5317743
Issued on: 05/31/1994
Inventor: Imai, et al.

Inventor

Assignee

Application

No. 395373 filed on 02/21/1995

US Classes:

712/241Loop execution

Examiners

Primary: Eng, David Y.

Attorney, Agent or Firm

Foreign Patent References

  • 1280862 JP. 11/13/1989
  • 261727 JP. 03/13/1990
  • 3218528 JP. 09/13/1991

International Class

G06F 009/45

Foreign Application Priority Data

1991-11-11 JP

Abstract

The present invention provides an apparatus for detecting possibility to process in parallel a program including a loop where iteration processing is executed comprising a simulation unit for simulating each iteration of the loop in the program, a variable storage unit for storing information based on the simulation as to a variable whose value is defined in a program statement in relation with information showing a location where in the program the value of the variable is defined, and a judgement unit for judging whether or not parallel processing is possible by referring to the variable storage unit for information of the location;The present invention further provides a program translation apparatus for generating a program applicable to parallel processing based on the detected possibility of executing the program in parallel comprising the simulation unit, the variable storage unit, the judgement unit, and the program generation means for generating the program applicable to parallel processing when it is judged by the judgement unit that parallel processing of the program is possible.

Other References

  • "Advanced Compiler Optimizations for Supercomputers", by David A. Padua and Michael J. Wolfe, Communications of the ACM, Dec. 1986, vol. 12, No. 12, pp. 1184-120
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