Computer logic simulation with dynamic modeling
August 8, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesSimulator system for logic design validation Hierarchical net list derivation system Logic circuit simulation method Simulation system Circuit simulation method for semiconductor device including field effect transistors Event-controlled LCC stimulation Simulation model generation from a physical data base of a combinatorial circuit Method of simulating the operation of a circuit having analog and digital circuit parts Analytical development and verification of control-intensive systems System for simultaneous, interactive presentation of electronic circuit diagrams and simulation data InventorsApplicationNo. 512600 filed on 08/08/1995US Classes:703/17Event-drivenExaminersPrimary: Teska, Kevin J.Assistant: Frejd, Russell W. Attorney, Agent or FirmInternational ClassG06F 009/455AbstractA method for improving the performance of a computer logic simulator in a computer system in which the operation of a logic design is simulated by converting a network list representative of the logic design into a simulator netlist and applying predetermined input vectors to the simulator netlist representative of the logic design in order to generate output vectors representative of the response of the simulator netlist. Portions of the network list are converted to dynamic device models in the form of executable code, which is assembled in a dynamic device model file. The remaining portions of the network list are converted to a simulator netlist, which is stored in a simulator netlist file. Both the dynamic device models and the simulator netlist are used to perform the simulation process. Since the dynamic device models are in the form of executable code, which can be directly read during the simulation process, the speed of operation of the simulation process is substantially increased, with a corresponding reduction in the total processing time required. In addition, the size of the simulator netlist is substantially reduced.Other References
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