Bus snoop method and apparatus for computer system having CPU with cache and main memory unit
April 19, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation Cache memory system which snoops an operation to a first location in a cache line and does not snoop further operations to locations in the same line Personal computer having memory system with write-through cache and pipelined snoop cycles Second level cache controller unit and system Multiprocessor cache abitration Patent #: 5426765 InventorsAssigneeApplicationNo. 229755 filed on 04/19/1994US Classes:711/146, Snooping710/107Bus access regulationExaminersPrimary: Shah, Alpesh M.Attorney, Agent or FirmForeign Patent References
International ClassG06F 013/14Foreign Application Priority Data1993-04-23 JPAbstractBus snoop method and apparatus for use in a computer system in which a CPU with cache is coupled to a main memory control unit for controlling a main memory unit through a bus snoop control unit, wherein when the CPU with cache occupies a bus at the time that an external bus master transfers data to the main memory unit, a transfer address for transfer of the data undergoes buffering in the bus snoop control unit and after the CPU with cache ends the execution of an instruction and opens a bus right, the bus snoop control unit transfers the data transfer address subject to buffering to the CPU with cache and a corresponding address recorded in the cache is canceled. | |
