Patent ReferencesSynchronizing mechanism for page replacement control Method for managing virtual memory to separate active and stable memory blocks Shadow memory system for storing variable backup blocks in consecutive time periods Separate content addressable memories for storing locked segment addresses and locking processor identifications for controlling access to shared memory System and method for preventing direct access data storage system data loss from mechanical shock during write operation System for updating data stored on a flash-erasable, programmable, read-only memory (FEPROM) based upon predetermined bit value of indicating pointers Patent #: 5392427 InventorAssigneeApplicationNo. 231019 filed on 04/21/1994US Classes:711/170, Memory configuring711/103, Programmable read only memory (PROM, EEPROM, etc.)711/162BackupExaminersPrimary: Kim, MatthewAttorney, Agent or FirmForeign Patent References
International ClassG06F 012/00AbstractIn a system for the management of non-volatile memories, to avoid losses of information during writing, the critical writing sequences are locked. A back-up information element is stored before the performance of the critical section. The lock is constituted by the bits of the allocation table that designate the location of the saved back-up information. The lock is erased at the end of a normal writing sequence. If there is an abnormal interruption of a writing operation during the critical section, then the lock remains locked. This is detected when the power is turned on again, and the writing is resumed utilizing the saved information elements. The lock and the saved information elements are in a variable zone of the memory, thus preventing memory fatigue in the event of intensive use. Furthermore, the management of the memory is original in that two different memory allocation strategies are used to enable the detection, by the allocation table, of the presence of an information element whose location is not known.Other References
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