Configurable XNOR/XOR element
Patent 5568067 Issued on October 22, 1996. Estimated Expiration Date: 
June 30, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
June 30, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent References 3439185 Exclusive or integrated logic circuits using complementary MOSFET technology Reduced parallel EXCLUSIVE or and EXCLUSIVE NOR gate Combinational static CMOS logic circuit Method and device for avoiding latent errors in a logic network for majority selection of binary signals Patent #: 5140594 InventorsAssigneeApplicationNo. 497007 filed on 06/30/1995US Classes:326/55, With field-effect transistor326/45, Complementary FET`s326/54Exclusive NORExaminersPrimary: Westin, Edward P.Assistant: Roseen, Richard Attorney, Agent or FirmInternational ClassesH03K 019/094H03K 019/21 AbstractA configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration. In an alternative embodiment, the XNOR/XOR logic element can be used in a full adder to provide the sum output. | |
