Method of fabricating non-volatile sidewall memory cell
Patent 5563083 Issued on October 8, 1996. Estimated Expiration Date: 
April 21, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.
April 21, 2015. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesVertical memory cell array and method of fabrication Process for fabricating a contactless floating gate memory array utilizing wordline trench vias Three dimensional famos memory devices and methods of fabricating Process for forming an electrically programmable read-only memory cell Patent #: 5382540 InventorApplicationNo. 426512 filed on 04/21/1995US Classes:438/259, Including forming gate electrode in trench or recess in substrate257/314, Variable threshold (e.g., floating gate memory device)257/E21.693, For vertical channel (EPO)257/E27.103, Electrically programmable ROM (EPO)257/E29.306Hot carrier injection from channel (EPO)ExaminersPrimary: Chaudhari, ChandraInternational ClassH01L 021/824.7AbstractA non-volatile memory cell and array of such cells is provided. The memory cell includes a single transistor floating gate cell fabricated on a sidewall of a silicon pillar etched into a silicon substrate. The memory cells are arranged in an array of rows extending in a bit line direction and columns extending in a word line direction. A substantially smaller cell and array size is realized by limiting the dimension of the pillar and the bit line in the word line direction to be the minimum line width as limited by the lithography. | |
