Computer network switching system with expandable number of ports
October 26, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesMethod for operating a packet bus for transmission of asynchronous and pseudo-synchronous signals Network protocol for integrating synchronous and asynchronous traffic on a common serial data bus Routing architecture for a multi-ring local area network Interconnection of communications networks Method and apparatus for bridging local area networks Method and apparatus for interfacing to a local area network Distributed load sharing Communications circuit having an interface for external address decoding Group address translation through a network bridge Communication processor for a packet-switched network InventorsApplicationNo. 330074 filed on 10/26/1994US Classes:370/352, Combined circuit switching and packet switching370/362, Bus switch370/391, Switching input signals having different aggregate bit rates370/444, With priority resolution370/461Arbitration for access between contending stationsExaminersPrimary: Safourek, Benedict V.Assistant: Rao, Seema S. Attorney, Agent or FirmInternational ClassesH04J 003/2695.2 95.3 95.1 AbstractA switching fabric circuit that provides on-the-fly switching of packets, an expandable number of ports, and the interconnection of heterogeneous LAN segments. The switching fabric circuit includes a switching link that comprises a switching bus and a plurality of packet processors, wherein each packet processor is coupled between the switching bus and a LAN segment. The switching bus is a time division multiple access (TDMA) bus, and arbitration for switching bus access is distinct from arbitration for access to the ports of the switching fabric circuit. Switching bus arbitration is done according to one of two priority levels, wherein high priority requests are guaranteed access to the switching bus during a synchronization period in which the high priority requests are made. This provides for guaranteed throughput and on-the-fly switching of packets. Port arbitration may be either uniport port arbitration or multiport port arbitration. Port arbitration is characterized by the transmission of a POE mask by a source port to a destination port and by the subsequent transmission of a DPA signal by the destination port to the source port. | |
