Caching FIFO and method therefor
September 17, 2013. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesThree port random access memory Semiconductor integrated circuit device Three port random access memory in a network bridge Personal computer having a local bus interface to a video circuit Data processing apparatus with self-emulation capability Crossbar interface for data communication network Multiprocessor software interface for a graphics processor subsystem employing partially linked dynamic load modules which are downloaded and fully linked at run time Apparatus and method for maintaining cache/main memory consistency utilizing a dual port FIFO buffer Method and apparatus for performing a read-write-modify operation in a VGA compatible controller Fast graphics control system capable of simultaneously storing and executing graphics commands Patent #: 5299309 InventorsAssigneeApplicationNo. 042306 filed on 04/02/1993US Classes:345/554, Multi-port memory345/531, Graphic display memory controller345/557, Cache345/558First in first out (i.e., FIFO)ExaminersPrimary: Powell, Mark R.Assistant: Chauhan, U. Attorney, Agent or FirmInternational ClassG06F 015/00AbstractA memory subsystem for use between a CPU and a graphics controller in a typical small computer system has a cache interface for the CPU and a FIFO interface for the graphics controller. This configuration optimizes the data transfers for both the CPU and the graphics controller, and allows both to operate in a manner generally asynchronous to each other. This caching FIFO provides enhanced performance by matching the interface to the unique data requirements of the devices accessing the data within the caching FIFO. For the CPU, the caching FIFO appears as a normal data cache. For the graphics controller, the caching FIFO appears as a normal dual port FIFO, which optimizes the highly sequential data transfers characteristic of graphics controllers. The simple design of the caching FIFO provides maximum performance for a minimum of gates, making the circuit well-suited to efficient implementation in silicon.Other References
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