Dual instruction set processor having a pipeline with a pipestage functional unit that is relocatable in time and sequence order
December 21, 2014. Estimated Expiration Date is calculated based on simple USPTO term provisions. It does not account for terminal disclaimers, term adjustments, failure to pay maintenance fees, or other factors which might affect the term of a patent.Patent ReferencesAddress translator Address translation buffer Emulator for non-fixed instruction set VLSI devices Computer providing flexible processor extension, flexible instruction set extension, and implicit emulation for upward software compatibility Emulator system utilizing a program counter and a latch coupled to an emulator memory for reducing fletch line of instructions stored in the emulator memory Method for detecting modified object code in an emulator Emulation method Processor capable of executing one or more programs by a plurality of operation units Extended floating point operations supporting emulation of source instruction execution Lubricated bearing retainer for X-ray tube InventorApplicationNo. 361017 filed on 12/21/1994US Classes:712/41, RISC710/240, ACCESS ARBITRATING712/208, INSTRUCTION DECODING (E.G., BY MICROINSTRUCTION, START ADDRESS GENERATOR, HARDWIRED)712/209Decoding instruction to accommodate plural instruction interpretations (e.g., different dialects, languages, emulation, etc.)ExaminersPrimary: Lall, Parshotam S.Assistant: Maung, Zarni Attorney, Agent or FirmInternational ClassG06F 009/30AbstractA CPU pipeline is able to process instructions from a complex instruction set computer CISC instruction set and from a reduced instruction set computer RISC set. A mode register is provided to indicate whether RISC or CISC instructions are currently being processed. Two instruction decode units are used, one for each instruction set. Compound CISC instructions flow from the decode pipestage to the address generate stage, then to an operand cache stage, and finally to an algebraic execute stage before the results are written back to the GPR register. When the CPU switches to RISC mode by clearing a mode bit in the mode register, the pipeline is re-arranged for processing the simpler RISC instructions. Two outputs are provided for the RISC instruction decoder. The first output is for simple execute-type instructions, while the second output is for load/store-type instructions, and connects to the address generate pipestage, which generates an address for the operand cache stage. These instructions are prevented from continuing to the execute stage by a mux. The mux normally connects the operand cache stage to the execute stage when CISC instructions are being processed, but the mux directly connects the second output of the RISC instruction decoder to the execute stage when the mode register enables RISC instruction decoding. This reduces the latency for RISC instructions by 1 or 2 clocks. An alternate embodiment re-arranges the pipeline dynamically as simple instructions are detected by the decode units. The preferred embodiment uses a fixed pipeline with the execute hardware relocatable to the D, C, or M pipestages. Thus the pipeline is optimized for both RISC and CISC instructions.Other References
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